Superconducting qubits are built, not found. Every deposition, every resist spin, every etch and clean leaves something behind at an interface, and that residue shows up later as coherence lost. The useful claim here is narrow: coherence tends to fall as process steps accumulate, and the mechanism is largely dielectric loss at surfaces. The evidence supports a correlation, not a law.

The Promise and the Fabrication Ledger

A transmon is a microwave circuit with a Josephson junction at its heart, and its quantum state lives in the phase across that junction. The design, published by Jens Koch and colleagues at Yale and Sherbrooke in 2007, deliberately traded charge sensitivity for a flatter energy landscape. That trade made transmons the workhorse of superconducting quantum computing, and it moved the dominant noise source somewhere else.

Once charge noise was suppressed, the limiting factor became the material environment. A transmon sits on a substrate, under dielectrics, beside a junction oxide, and inside a package. Each of those surfaces can host defects that absorb and emit energy at the qubit frequency. Fabrication is the process of creating those surfaces, so fabrication is where the coherence budget gets spent.

It helps to think of a process run as a ledger rather than a recipe. Each step deposits or removes material, and each one also deposits damage: adsorbed water, organic residue, subsurface oxide, interfacial roughness. The ledger is not additive in a simple way, which is exactly why process engineers argue about which line item dominates.

Where Coherence Actually Leaks Away

Modern transmon lifetimes are usually quoted in the tens to hundreds of microseconds, and the spread within a single chip can be substantial. Energy relaxation is commonly dominated by dielectric loss, meaning the qubit's microwave field samples a material with a lossy response. The field is not confined to the superconducting metal, which is comparatively clean.

It leaks into substrate surfaces, into the native oxide on the metal, into resist residue left in trenches, and into the junction's own tunnel barrier. Two-level systems in those amorphous regions can resonate with the qubit and take energy away. The density of such systems is a material property, and it is set during processing.

The loss is also frequency-dependent in a way that matters for design. Two-level systems have a broad distribution of transition energies, so a qubit parked at one frequency may sit in a dense patch of them while a neighbouring qubit a few hundred megahertz away sits in a sparse one. The same interface can be kind to one device and unkind to the next, which is part of why a wafer map of coherence times so rarely looks like a smooth gradient.

This is why a qubit can look excellent in one fabrication batch and mediocre in the next with no design change. The circuit is identical; the interfaces are not. A related piece on this site about how section thickness changes what imaging finds makes the same general point about preparation shaping results.

Tracing Losses to Specific Process Steps

Deposition sets the metal's grain structure and the roughness of its surface. Lithography leaves polymer behind, and the removal step matters as much as the patterning. Etching creates sidewalls and can redeposit material. Cleaning can introduce new chemistry even as it removes old contamination. Each contributes a measurable, if hard to isolate, loss channel.

Oxygen plasma ashing is a frequent suspect. It strips resist effectively, but it can oxidize the metal surface and leave a modified layer that later steps do not fully remove. Josephson junction oxidation conditions, including oxygen pressure and exposure time, set the barrier's quality and the junction's subgap behavior. Those parameters are often tuned empirically rather than from first principles, and the window that produces good junctions can be narrow enough that a small drift in pressure shifts the resistance distribution noticeably across a wafer.

Substrate choice carries its own trade-off. Silicon and sapphire are both common, and each has advocates. Sapphire tends to offer lower microwave loss in the bulk, while silicon benefits from a mature supply chain and easier integration with the rest of the process. Neither wins outright, because the interface a fab can produce reliably on a given substrate often matters more than the bulk properties the datasheet quotes.

Room-temperature probing is a poor predictor of millikelvin performance. A junction that measures acceptably at 300 kelvin can show excess subgap current at 10 millikelvin, because the relevant defects only reveal themselves at low energy. This gap between quick checks and cryogenic truth is one reason process improvements travel slowly between labs.

What the Evidence Does and Does Not Show

The correlation between more process steps and lower coherence is real in many published comparisons, but it is confounded. Longer processes tend to involve more handling, more exposure to atmosphere, and more chances for contamination. Step count is a proxy for cumulative interface damage, not a cause in itself.

The strongest objection comes from foundries, where highly standardized, high-step-count processes produce qubits with competitive coherence. A clean, well-controlled long process can beat a sloppy short one. Anyone treating step count as a design rule will be misled, and the device-to-device spread within a wafer complicates attribution further.

There is also a reporting problem. Papers often quote the best device on a chip rather than the median, which flatters process comparisons. A group that reports a single device at the high end of its distribution and a competitor that reports a median are not making the same claim, even when the numbers look comparable in a table. The reproducibility question is familiar to anyone following research infrastructure debates, as this site has noted on code repositories preserving the software results depend on; the underlying issue is the same, namely that the conditions producing a result are often undocumented.

Why the Gap Between Lab and Fab Matters

Academic cleanrooms and industrial foundries run different equipment, different chemistries, and different contamination controls. A process that works in a shared university facility may not transfer, and a foundry process may not permit the experimental variations a research group needs. Scaling to many qubits demands uniformity across a wafer, which tightens every tolerance.

The economics push in the same direction. A research cleanroom can afford to babysit a single wafer through a delicate step; a production line cannot, so it optimizes for a process window wide enough to survive ordinary drift. That difference in what counts as acceptable variation shapes which loss channels get engineered out and which get tolerated.

Coherence gains in recent years have come mostly from incremental process work: better substrate cleaning, improved junction oxidation, redesigned packages that reduce substrate loss. These are unglamorous improvements, and they are hard to publish as breakthroughs. The field's progress depends on them anyway.

A useful comparison is with the way model organism findings outpace the grants behind them: the visible output moves faster than the infrastructure that supports it, and the infrastructure is where the fragility sits.

Practical Steps for Process Control

Audit each fabrication step for its dielectric loss contribution rather than its nominal function. A cleaning step that removes resist but oxidizes metal is a net loss if the oxide dominates the qubit's field overlap. Measure the interface, not the recipe.

Track coherence across deliberate process splits, with enough devices per split to report a median and a spread. A single best device tells you what is possible; a distribution tells you what is reproducible, and reproducibility is what scales.

• Characterize interfaces with low-energy techniques where available, since room-temperature transport misses the defects that matter at millikelvin.
• Record oxidation pressure, exposure time, resist chemistry, and ashing conditions alongside every coherence number you publish.
• Prefer millikelvin-compatible diagnostics or in-situ monitoring over end-of-line room-temperature probing when attributing a loss channel.
• Compare process variants on the same wafer run so that handling and contamination are held roughly constant.

The practical priority is interface characterization over step counting. A process with many steps and clean interfaces will outperform a short process with a damaged surface, and the only way to know which you have is to measure the surface. That measurement is the part most often skipped.